linux – 上下文切换的开销是什么？

发布时间：2020-12-13 19:33:42 所属栏目：Linux 来源：网络整理

导读：本来我相信上下文切换的开销是TLB被刷新.不过我刚刚看到维基百科： http://en.wikipedia.org/wiki/Translation_lookaside_buffer In 2008,both Intel (Nehalem)[18] and AMD (SVM)[19] have introduced tags as part of the TLB entry and dedicated hardwar

本来我相信上下文切换的开销是TLB被刷新.不过我刚刚看到维基百科：

http://en.wikipedia.org/wiki/Translation_lookaside_buffer

In 2008,both Intel (Nehalem)[18] and AMD (SVM)[19] have introduced
tags as part of the TLB entry and dedicated hardware that checks the
tag during lookup. Even though these are not fully exploited,it is
envisioned that in the future,these tags will identify the address
space to which every TLB entry belongs. Thus a context switch will not
result in the flushing of the TLB – but just changing the tag of the
current address space to the tag of the address space of the new task.

以上是否确定了较新的Intel CPU,TLB在上下文切换中不会被刷新？

这是否意味着现在在上下文切换中没有真正的开销？

(我正在努力了解上下文切换的性能损失)

解决方法

由于维基百科知道 in its Context switch文章,“上下文切换是存储和恢复进程的状态(上下文)的过程,以便稍后可以从同一点继续执行.我将假设在同一个操作系统的两个进程之间进行上下文切换,而不是用户/内核模式转换(syscall),其速度要快得多,不需要任何TLB刷新.

因此,操作系统内核需要大量的时间来将当前正在运行的进程的执行状态(全部,特别是寄存器和许多特殊控制结构)保存到内存中,然后加载其他进程的执行状态(从内存读入) .如果需要,TLB刷新将为交换机添加一些时间,但这只是总开销的一小部分.

如果您想查找上下文切换延迟,则具有LAT_CTX测试http://www.bitmover.com/lmbench/lat_ctx.8.html的lmbench基准测试工具http://www.bitmover.com/lmbench/

我找不到nehalem的结果(在phoronix套件中有lmbench吗？),但对于core2 and modern Linux上下文切换可能需要5-7微秒.

还有对于上下文切换具有1-3微秒的低质量测试http://blog.tsunanet.net/2010/11/how-long-does-it-take-to-make-context.html的结果.不能从他的结果中获得不冲洗TLB的确切效果.

更新 – 您的问题应该是关于虚拟化,而不是关于进程上下文切换.

该公司表示,their article about Nehalem“内部Nehalem：英特尔的未来处理器和系统”TLBs,页表和同步化“2008年4月2日,David Kanter表示,Nehalem向TLB增加了VPID,使虚拟机/主机交换机(vmentry / vmexit)更快：

Nehalem’s TLB entries have also changed subtly by introducing a “Virtual Processor ID” or VPID. Every TLB entry caches a virtual to physical address translation … that translation is specific to a given process and virtual machine. Intel’s older CPUs would flush the TLBs whenever the processor switched between the virtualized guest and the host instance,to ensure that processes only accessed memory they were allowed to touch. The VPID tracks which VM a given translation entry in the TLB is associated with,so that when a VM exit and re-entry occurs,the TLBs do not have to be flushed for safety. …. The VPID is helpful for virtualization performance by lowering the overhead of VM transitions; Intel estimates that the latency of a round trip VM transition in Nehalem is 40% compared to Merom (i.e. the 65nm Core 2) and about a third lower than the 45nm Penryn.

另外,你应该知道,在这个问题中引用的片段中,“[18]”链接是“G. Neiger,A. Santoni,F. Leung,D. Rodgers和R. Uhlig.英特尔虚拟化技术：硬件支持高效的处理器虚拟化,Intel Technology Journal,10(3)“,因此这是有效的虚拟化(快速客户主机交换机)的功能.

（编辑：李大同）

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