zigbee cc2530地址空间 layout 和flash操作

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2.2.2 CPU Memory Space
cpu存储空间（以下叫地址空间）

XDATA memory space . The XDATA memory map is given in Figure 2-1.
Xdata地址空间，64KB
The SRAM is mapped into address range of 0x0000 through (SRAM_SIZE – 1).
sram被映射在地址空间的的0-SRAM_SIZE-1
The XREG area is mapped into the 1-KB address range (0x6000–0x63FF). These registers are additional
registers,effectively extending the SFR register space. Some peripheral registers and most of the radio
control and data registers are mapped in here.
XREG寄存器被映射在0x6000–0x63FF。XREG寄存器是额外的寄存器，是SFR的补充。主要用于射频控制等。
The SFR registers are mapped into address range (0x7080–0x70FF).
SFR寄存器被映射在0x7080–0x70FF。
The flash information page (2 KB) is mapped into the address range (0x7800–0x7FFF). This is a read-only
area and contains various information about the device.
flash信息页被映射在 0x7080–0x70FF。只读。
The upper 32 KB of the XDATA memory space (0x8000–0xFFFF) is a read-only flash code bank (XBANK)
and can be mapped to any of the available flash banks using the MEMCTR.XBANK[2:0] bits.
flash bank的任意一页可以映射在0x8000–0xFFFF，这个区域是XBANK。
The mapping of flash memory,SRAM,and registers to XDATA allows the DMA controller and the CPU
access to all the physical memories in a single unified address space.
这种将SRAM,falsh和寄存器映射到XDATA的地址映射方式，可以使得DMA和CPU在一个统一的地址空间中，寻址所有物理内存。




CODE memory space. ?The CODE memory space is 64 KB and is divided into a common area
(0x0000–0x7FFF) and a bank area ( 0x8000–0xFFFF) as shown in Figure 2-2. The common area is
always mapped to the lower 32 KB of the physical flash memory (bank 0). The bank area can be mapped
to any of the available 32-KB flash banks (from 0 to 7). The number of available flash banks depends on
the flash size option. Use the flash-bank-select register,FMAP,to select the flash bank. On 32 KB
devices,no flash memory can be mapped into the bank area. Reads from this region return 0x00 on these

devices.

code地址空间，64KB
被划分为一个通用区（启动区）0x0000–0x7FFF和一个bank区域0x8000–0xFFFF。bank区域可以映射flash的的任意一个可用bank.
cpu启动时从CODE地址空间的0地址处取指令。

To allow program execution from SRAM,it is possible to map the available SRAM into the lower range of
the bank area from 0x8000 through (0x8000+SRAM_SIZE–1). The rest of of the currently selected bank is
still mapped into the address range from (0x8000 + SRAM_SIZE) through 0xFFFF). Set the

MEMCTR.XMAP bit to enable this feature.
为了可以从SRAM中执行程序，可以将SRAM映射到CODE的bank区域0x8000+SRAM_SIZE–1。这样在启动区放置一条跳转代码，就可以直接跳转到SRAM执行了。

DATA memory space.The 8-bit address range of DATA memory is mapped into the upper 256 bytes of
the SRAM,i.e.,the address range from (SRAM_SIZE-256) through (SRAM_SIZE-1).
DATA地址空间，256B
位于SRAM的最上边的256字节。比如寄存器R0-R7都要通过DATA地址空间访问。

SFR memory space.?The 128-entry hardware register area is accessed through this memory space. The
SFR registers are also accessible through the XDATA address space at the address range (0x7080 –
0x70FF). Some CPU-specific SFR registers reside inside the CPU core and can only be accessed using
the SFR memory space and not through the duplicate mapping into XDATA memory space. These
specific SFR registers are listed in SFR Registers .
128个硬件寄存器通过这块内存访问，部分SFR寄存器也可以通过XDATA地址空间0x7080 – 0x70FF访问，如下
P0 0x80 CPU Port 0. Readable from XDATA (0x7080).
P1 0x90 CPU Port 1. Readable from XDATA (0x7090).
P2 0xA0 CPU Port 2. Readable from XDATA (0x70A0).
一些cpu特定的寄存器位于cpu核内部，只能通过SFR地址空间访问而不能通过XDATA地址空间访问。大部分SFR都不能通过XDATA访问。

综上，4个地址空间
XDATA,几乎所有的物理存储器都可以映射到这个地址空间之上，包括sram,flash,xreg,information fage,少部分SFR。
CODE，falsh可以映射到其上，SRAM也可以。
DATA，只有SRAM的最高256字节可以映射其上。
SFR，大部分的SFR寄存器都使用SFR地址空间寻址。

注意：DATA地址空间和SRAM内存似乎有点混论，只要记住data地址空间就是用来访问SRAM的最高256字节的。
2.2.3 Physical Memory
物理存储器

RAM. All devices contain static RAM. At power on,the content of RAM is undefined. RAM content is
retained in all power modes.
SRAM可以映射到XDATA地址空间0起始地址，也可以映射到CODE地址空间的上半截。

Flash Memory. The on-chip flash memory is primarily intended to hold program code and constant data.
The flash memory has the following features:
· Page size: 2 KB
· Flash-page erase time: 20 ms
· Flash-chip (mass) erase time: 20 ms
· Flash write time (4 bytes): 20 ms
· Data retention (at room temperature): 100 years
· Program/erase endurance: 20,000 cycles
falsh可以映射到CODE地址空间和XDATA地址空间的XBANK
SFR Registers.?The special function registers (SFRs) control several of the features of the 8051 CPU
core and/or peripherals. Many of the 8051 core SFRs are identical to the standard 8051 SFRs. However,
there are additional SFRs that control features that are not available in the standard 8051. The additional
SFRs are used to interface with the peripheral units and RF transceiver.
可以使用SFR地址空间访问，部分寄存器也可以使用XDATA地址空间访问。

The Information Page?is a 2 KB read-only region that stores various device information. Among other
things it contains a unique IEEE address from the TI range of addresses. It is stored with the least
significant byte first at XDATA address 0x780C. A separate design note will be published that details the
contents of the information page.
SFR Registers. The special function registers (SFRs) control several of the features of the 8051 CPU
core and/or peripherals. Many of the 8051 core SFRs are identical to the standard 8051 SFRs. However,0)">保存了设备信息比如IEEE地址。
只能使用XDATA地址空间访问。

XREG Registers.?The XREG registers are additional registers in the XDATA memory space. These
registers are mainly used for radio configuration and control. A complete description of each register is
given in Section 3.6. Table 2-2 gives a descriptive overview of the register address space.
只能通过XDATA地址空间访问

另外：
arm（9,11）执行指令时，是从ram中取代码的。所以开机时需要先将程序代码从nandflash搞到ram中去(如果是norflash，arm9,11也可以直接执行之）。
单片机执行指令时，是从flash中取代码的。
一般在ram中运行很快，但是单片机的ram比较小，一般不足以放置一个较大的代码，所以就直接从flash中运行了。
cc2530基于51内核，数据存储器ram和代码存储器flash分开编址，cpu上电时从代码存储器flash的0地址处开始执行。
arm内核数据存储器ram和代码存储器ram统一编址，cpu上电时从0地址开始执行。一般flash的0地址会被映射到不同的物理存储器上。

flash寿命-http://e2e.ti.com/support/low_power_rf/f/155/t/36547.aspx
For?CC2530?and?CC2531,the flash can handle 20,000 erase cycles.

cc2530读flash
HalFlashRead
cc2530共计有256KBflash,每2KB划分为1page,每16page划分为1 bank
如图

在读取flash中数据的时候，首先要知道是读的哪个第几个bank中的数据，因为要把对应的flash bank映射到xdata地址空间的XBANK上，在xdata地址空间去读。映射bank的时候需要配置寄存器MEMCTR为相应的bank号。

协议栈NVITEM使用的flash位于的地址
#define OSAL_NV_PAGE_BEG ? ? ? ?HAL_NV_PAGE_BEG//=126-6+1=121

#define OSAL_NV_PAGE_END ? ? ? (OSAL_NV_PAGE_BEG + OSAL_NV_PAGES_USED - 1)//=121+6-1=126

即0x3C800---0x3F800-1
另外，
在f8w2530.xcl中有对flash逻辑地址作如下定义