OK6410（256M RAM ，2G SLC NAND）Uboot-2013-04移植

1. /*?NAND chip page size?*/
   
2. #define CONFIG_SYS_NAND_PAGE_SIZE ? ?4096
   
3. *?NAND chip block size?/
   
4. #define CONFIG_SYS_NAND_BLOCK_SIZE ??(128?*?4096)
   
5. *?NAND chip page per block count?/
   
6. #define CONFIG_SYS_NAND_PAGE_COUNT ? 128

*

?*?(C)?Copyright 2006 DENX Software Engineering

?*

?*?Implementation?for?U-Boot 1.1.6 by Samsung

?)?Copyright 2008

?*?Guennadi Liakhovetki,?DENX Software Engineering<lg@denx.de>

?*?See file CREDITS?for?list of people who contributed?to?this

?*?project.

?*?This program?is?free software;?you can redistribute it?andor

?*?modify it under the terms of the GNU General?Public?License as

?*?published by the Free Software Foundation;?either version 2 of

?*?the Licenseor?(at your?option)?any later versionis?distributed?in?the hope that it will be useful

?*?but WITHOUT ANY WARRANTY;?without even the implied warranty of

?*?MERCHANTABILITY?or?FITNESS?FOR?A PARTICULAR PURPOSE.?See the

?*?GNU General?Public?License?for?more details*?You should have received a copy of the GNU General?Public?License

?*?along with this program;?if?notto?the Free Software

?*?Foundation.?Suite 330*?MA 02111-1307 USA

?/

#include?<common.h>

#include?<nand>

#include?<linux/mtd/nand>

#ifdef CONFIG_S3C6400

#include?<asm/arch/s3c6400>

#else

#include?/s3c6410>

#endif

#include?/io/errno>

#define MAX_CHIPS????2

static?int?nand_cs[MAX_CHIPS]?=?{0};

#ifdef CONFIG_NAND_SPL

#define printf(arg)?do?{}?while?(0)

#endif

*?Nand flash definition values by jsgood?/

#ifdef S3C_NAND_DEBUG

Function?to?print out oob buffer?for?debugging

?*?Written by jsgood

?/

static void print_oob(const?char?*header*mtd{

????int?i;

????struct nand_chip?*chip?=?mtd->priv;

????printf("%s:t");

????for?(i?=?0;?i?<?64;?i+)

????????printf"%02x ">oob_poi[i]"n";

}

#endif?*?S3C_NAND_DEBUG?/

static void s3c_nand_select_chip(struct mtd_info?int?chipint?ctrl?=?readl(NFCONT;

????switch?(chip{

????case?-1:

????????ctrl?|=?6;

????????break;

????case?0&~2case?1~4;

????default:

????????return}

????writel(ctrl}

*?Hardware specific access?to?control-lines?function

?/

static void s3c_nand_hwcontrolint?cmdint?ctrl{

????struct nand_chip?*this?(ctrl?&?NAND_CTRL_CHANGE{

????????&?NAND_CLE)

????????????this>IO_ADDR_W?(void __iomem?)NFCMMD;

????????else?&?NAND_ALE)NFADDRelse

????????????this)NFDATA&?NAND_NCE)

????????????s3c_nand_select_chip(mtdint?)thiselse

????????????s3c_nand_select_chip}

????(cmd?!=?NAND_CMD_NONE)

????????writeb(cmd>IO_ADDR_Wfor?checking device ready pin

?/

static?int?s3c_nand_device_ready*mtdinfo{

????return?(readl(NFSTAT&?NFSTAT_RnB}

#ifdef CONFIG_SYS_S3C_NAND_HWECC

*?This?function?is?called before encoding ecc codes?to?ready ecc engine/

?

#if?defined(CONFIG_NAND_BL1_8BIT_ECC&?(defined(CONFIG_S3C6410|?defined(CONFIG_S3C6430)

?*

??*?jsgood:?Temporary 8 Bit H/W ECC supports?for?BL1?(6410/6430 only)

??/

?int?cur_ecc_mode=0*

?????for?checking ECCEncDone?in?NFSTAT

?????*?Written by jsgood

?????/

????static void s3c_nand_wait_enc(void)

????&?NFSTAT_ECCENCDONE}

????}

????

????for?checking ECCDecDone?/

????static void s3c_nand_wait_dec&?NFSTAT_ECCDECDONE}

??

?static void s3c_nand_wait_ecc_busy_8bit{

?????(NF8ECCERR0&?NFESTAT0_ECCBUSY}

?}

?void s3c_nand_enable_hwecc_8bitint?mode{

????u_long nfcont;

????cur_ecc_mode?=?mode*?8 bit selection?/

????nfconf?(NFCONF;

????nfconf?~(0x3?<<?23;

????nfconf?(0x1?;

????writel(nfconf*?Initialize?&?unlock?/

????nfcont?;

????nfcont?=?NFCONT_INITECC~NFCONT_MECCLOCK(mode?==?NAND_ECC_WRITE)

????????nfcont?=?NFCONT_ECC_ENC=?NAND_ECC_READ~NFCONT_ECC_ENC(nfcont}

int?s3c_nand_calculate_ecc_8bitconst?u_char?*dat*ecc_code?nfm8ecc1?nfm8ecc3*?Lock?=?NFCONT_MECCLOCK;

????writel(cur_ecc_mode?)

????????s3c_nand_wait_dec{

????????s3c_nand_wait_enc;

????????nfm8ecc0?(NFM8ECC0;

????????nfm8ecc1?(NFM8ECC1;

????????nfm8ecc2?(NFM8ECC2;

????????nfm8ecc3?(NFM8ECC3;

????????ecc_code[0=?nfm8ecc0?&?0xff;

????????ecc_code[1(nfm8ecc0?>>?8[2>?16[3>?24[4=?nfm8ecc1?[5(nfm8ecc1?[6[7[8=?nfm8ecc2?[9(nfm8ecc2?[10[11[12=?nfm8ecc3?}

????return 0}

int?s3c_nand_correct_data_8bit*read_ecc*calc_eccint?ret?;

????u_long nf8eccerr0?nf8eccerr2?nfmlc8bitpt1;

????u_char err_type;

????s3c_nand_wait_ecc_busy_8bit;

????nf8eccerr0?;

????nf8eccerr1?(NF8ECCERR1;

????nf8eccerr2?(NF8ECCERR2;

????nfmlc8bitpt0?(NFMLC8BITPT0;

????nfmlc8bitpt1?(NFMLC8BITPT1;

????err_type?(nf8eccerr0?>?25&?0xf*?No?errorIf?free page?(all 0xff/

????>?29&?0x1)

????????err_type?(err_typecase?8:?*?8 bit?error?(Correctable/

????????dat[(nf8eccerr2?>?22&?0x3ff]?^(nfmlc8bitpt1?;

????????printk"s3c-nand: %d bit(s) error detected,corrected successfullyn"case?7*?7 bit?>?11case?6*?6 bit?[nf8eccerr2?case?5*?5 bit?(nf8eccerr1?case?4*?4 bit?(nfmlc8bitpt0?case?3*?3 bit?[nf8eccerr1?case?2*?2 bit?>?15;

????*?1 bit?/

????????printk;

????????dat[nf8eccerr0?;

????????ret?=?err_type/

????????ret?}

????return ret}

void s3c_nand_write_page_8bit*chip

??????????????????????????????const?uint8_t?*buf=?512;

????int?eccbytes?=?13int?eccsteps?>writesize?/?eccsize;

????uint8_t?*ecc_calc?=?chip>buffers>ecccalc*p?=?buf;?eccsteps=?eccbytes=?eccsize{

????????s3c_nand_enable_hwecc_8bit;

????????chip>write_buf?eccsize;

????????s3c_nand_calculate_ecc_8bit&ecc_calc<?eccbytes?)

????????chip+24=?ecc_calc;

????chip>oobsizeint?s3c_nand_read_page_8bit

????????????????????????????uint8_t?int?col?*?Step1:?read whole oob?/

????col?>writesize>cmdfunc?col>read_buf;

????col?{

????????chip;

????????s3c_nand_enable_hwecc_8bit>oob_poi?+?24?+?-?eccsteps*?eccbytes?0;

????????stat?=?s3c_nand_correct_data_8bit;

????????(stat?)

????????????mtd>ecc_stats.failed;

????????col?=?eccsize?+?1?/

#endif

static void s3c_nand_enable_hwecc*?The original driver used 4-bit ECC?for?"new"?MLC chips.efor

?????*?those with non-zero ID:2for?ST

?????(Numonyx)?chips

?????/

????nfconf?~NFCONF_ECC_4BIT;

????

????writelis?called immediately after encoding ecc codesfunction?returns encoded ecc codesint?s3c_nand_calculate_ecc

???????????????? u_char?;

????nfmecc0?(NFMECC0;

????ecc_code=?nfmecc0?;

????ecc_code(nfmecc0?;

????

????return 0function?determines whether read data?is?good?If?SLCto?controller before reading status bitIf?MLCis?already?setis?neededIf?status bit?is?goodIf?correctable errors occureddo?thatIf?uncorrectable errors occuredint?s3c_nand_correct_data;

????u_long nfestat0?nfmeccdata1?repaired*?SLC:?Write ecc?to?compare?/

????nfmeccdata0?(calc_ecc<?16|?calc_ecc;

????nfmeccdata1?(nfmeccdata0(nfmeccdata1*?Read ecc status?/

????nfestat0?(NFESTAT0;

????err_type?=?nfestat0?&?0x3:

????????*

?????????)

?????????(nfestat0?>?7&?0x7ff????:error?byte number

?????????>?4&?0x7????error?bit number

?????????/

????????err_byte_addr?&?0x7ff;

????????repaired?=?dat[err_byte_addr]?^?(1?<?&?0x7;

????????printf"S3C NAND: 1 bit error detected at byte %ld. "

?????????"Correcting from 0x%02x to 0x%02x...OKn"

???????? err_byte_addr;

????????dat=?repaired;

????????ret?=?1*?Multiple?*?ECC area?/

????????printf"S3C NAND: ECC uncorrectable error detected. "

?????????"Not correctable.n"*?CONFIG_SYS_S3C_NAND_HWECC?/

*?Board-specific NAND initialization.?The following members of the

?*?argument are board-specific?(per include/linux:

?-?IO_ADDR_R?:?address?to?read the 8 I/O lines of the flash device

?-?IO_ADDR_Wto?write the 8 I-?hwcontrol:?hardwarespecific?for?accesing control-lines

?-?dev_readyfor?accesing device ready/busy line

?-?enable_hweccto?enable?(reset)?hardware ecc generator.?Must

?*?only be provided?if?a hardware ECC?is?available

?-?eccmode:?mode of ecc

?-?chip_delay:?chip dependent delay?for?transfering data from?array?to

?*?read regs?(tR-?options:?various chip options.?They can partly be?set?to?inform

?*?nand_scan about special functionality.?See the defines?for?further

?*?explanation

?*?Members with a?"?"?were?not?in?the merged testing-NAND branch*?so they are?set?here either/

int?board_nand_init(struct nand_chip?*nand{

????static?int?chip_n(chip_n?=?MAX_CHIPS)

????????return?-ENODEV;

????NFCONT_REG?(NFCONT_REG?~NFCONT_WP|?NFCONT_ENABLE?|?0x6;

????nand>IO_ADDR_R????????;

????nand>IO_ADDR_W????????>cmd_ctrl????????=?s3c_nand_hwcontrol>dev_ready????????=?s3c_nand_device_ready>select_chip????=?s3c_nand_select_chip>options????????;

#ifdef CONFIG_NAND_SPL

????nand>read_byte????????=?nand_read_byte>write_buf????????=?nand_write_buf>read_buf????????=?nand_read_buf;

#endif

#ifdef CONFIG_SYS_S3C_NAND_HWECC

????#ifdef CONFIG_NAND_BL1_8BIT_ECC

????printf"USE HWECC 8BITn";/zxd

????nand>ecc.hwctl????????=?s3c_nand_enable_hwecc_8bit.calculate????=?s3c_nand_calculate_ecc_8bit.correct????.read_page?=?s3c_nand_read_page_8bit.write_page?=?s3c_nand_write_page_8bit;

????#else

????printf"USE HWECC Defaultn"=?s3c_nand_enable_hwecc=?s3c_nand_calculate_ecc=?s3c_nand_correct_data;

????#endif

????If?you?get?more than 1 NAND-chip with different page-sizes?on?the

?????*?board one?dayget?more complicated.

?????/

????nand.mode????????=?NAND_ECC_HW.size????????=?CONFIG_SYS_NAND_ECCSIZE.bytes????????=?CONFIG_SYS_NAND_ECCBYTES;

????printf"ECC Size:%d ECC Bytes:%dn".size.bytes/zxd????

#else

????nand=?NAND_ECC_SOFT;

#endif?!?CONFIG_SYS_S3C_NAND_HWECC?/

????nand>priv????????=?nand_cs?+?chip_n;

????return 0}

!read?&?s?NULL?!strcmp(s".uboot"&?nand=?4096{

????????????????rwsize=4096;

????????????????nand_write(nand&rwsize(u_char?)addr;

????????????????off;

????????????????addr=2048;

????????????????rwsize=?CONFIG_SYS_NAND_U_BOOT_SIZE?-?8*1024;

????????????????ret?=?nand_write;

#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE

#define CONFIG_BOOTCOMMAND?"nand read 0x50018000 0x60000 0x1c0000;"?

????????????????????????????"bootm 0x50018000"

#endif

#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE

#ifdef CONFIG_BOOT_SD

#define CONFIG_BOOTCOMMAND?"fatload mmc 0 50008000 u-boot-nand.bin;"?????????????????????????????"nand erase.chip;"?????????????????????????????"nand write.uboot 50008000 0 0"

#else

#define CONFIG_BOOTCOMMAND?"nand read 0x50008000 0x100000 0x500000;"?????????????????????????????"bootm 50008000"

#endif

#endif

#define CONFIG_SYS_NAND_U_BOOT_OFFS?(16?*?1024)??*?Offset?to?RAM U-Boot image?/

#define CONFIG_SYS_NAND_U_BOOT_SIZE?(496?*?Size of RAM U/

#(CONFIG_NAND_SPL)

*?deprecated/

ldr sp(CONFIG_SYS_INIT_SP_ADDR后面添加

bss_clean:

? ? ? ? ?cmp r0

? ? ? ? ?strlo r2[r0]

? ? ? ? ?addlo r0#4

? ? ? ? ?blo bss_clean

? ? ? ? ?ldr pc=nand_boot