WINCE - MLC型 NANDFLASH TWO_PLANE PAGE PROGRAM\READ
/***********************************************************************/ /* ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Bryan Wang ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?*/ /* ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?2013-8-1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?*/ /***********************************************************************/ 以K9GAG08U0D为例,整理TWO-PLANE读写操作。 1、TWO_PLANE PAGE PROGRAM Two-Plane page program is an extension of page program,for a single plane with 4314 byte data registers. Since the device is equiped with two memory planes,activating the two sets of 4314 bytes data registers enables a simultaneous programing of two pages. After writing the first set of data up to 4314 byte into the selected data registers via cache registers,Dummy Page Program commad(11h) instead of actual Page Program command(10h) is inputted to finish data-loading of the first plane. Since no programming process is involved,R//B remains in Busy state for a short period of time(tDBSY). Read Status command(70h) may be issued to find out when the device returns to Ready state by polling the Read/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the 81h command and address sequences. After inputting data for the last plane,actual True Page Program(10h) instead of dummy Page Program command(11h) must be followed to start the programing process. The operation of Ready/Busy and Read Status is the same as that of Page Program. Although two planes are programmed simultaneously,pass/fail is not availalbe for each page when the program operation completes. Status bit of I/O is set to "1" when any of the page fails.
2、TWO-PLANE PAGE READ Two-Plane Page Read is an extension of Page Read,for single plane with 4314 byte data registers. Since the dvice is equipped with two memory planes,activating the two sets of 4314 bytes data registers enables a random read of two pages. Two-Plane Page Read is initiated by repeating command 60h followed by three address cycles twice. In this case, only same page of same block can be selected from each time. After Read Confirm command(30h) the 8628 bytes of data within the selected two page are transferred to the cache registers via data registers in less than 60us(tR). The system controller can detect the completion of data transfer(tR) by monitoring the output of R/B pin. Once the data is loaded into the cache registers,the data output of first plane can be read out by issuing command 00h with Five Address Cycles,command 05h with two column address and finally E0h. The data output of second plane can be read out using the identical command sequences.
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